The present invention relates to a semiconductor device and a manufacturing method thereof, and is preferably applicable to, for example, a semiconductor device having a memory element, and a manufacturing method thereof.
As electrically writable/erasable nonvolatile semiconductor storage devices, EEPROMs (Electrically Erasable and Programmable Read Only Memories) have been widely used. The storage devices typified by currently and widely used flash memories have conductive floating gate electrodes surrounded by an oxide film, or trapping insulation films under gate electrodes of MISFETs. The storage devices use charge accumulation states at the floating gates or the trapping insulation film as stored information, and read out the information as a threshold value of each transistor. The trapping insulation film denotes an insulation film capable of accumulating electric charges. As one example thereof, mention may be made of a silicon nitride film. Injection/discharge of electric charges into such charge accumulation regions causes each MISFET (Metal Insulator Semiconductor Field Effect Transistor) to be shifted in threshold value and to operate as a storage element. Such a memory has the following advantages: use of a trapping insulation film such as a silicon nitride film as a charge accumulation region leads to more excellent data holding reliability because electric charges are accumulated discretely as compared with the case where a conductive floating gate is used as a charge accumulation region; further, the excellent data holding reliability can reduce the film thicknesses of the oxide films over and under the silicon nitride film, which enables a lower voltage for write/erase operation; and other advantages.
Japanese Unexamined Patent Application Publication No. 2015-53474 (Patent Document 1) describes the technology of applying a high dielectric constant insulation film to a gate insulation film for a memory element.